{"id":3391,"date":"2021-05-31T17:07:22","date_gmt":"2021-05-31T20:07:22","guid":{"rendered":"https:\/\/araripe.com.br\/?post_type=_servicos&#038;p=3391"},"modified":"2022-10-24T15:11:14","modified_gmt":"2022-10-24T18:11:14","slug":"integrated-circuit-layout-design-protection","status":"publish","type":"_servicos","link":"https:\/\/araripe.com.br\/?_servicos=integrated-circuit-layout-design-protection&lang=en","title":{"rendered":"Integrated Circuit Topography"},"content":{"rendered":"<p>Popularly known as \u201cChip\u201d. It is set of related images codified under any means or form to configure three-dimensionally the layers which compose an integrated circuit. Each image represents the geometric arrangement of the surface of the integrated circuit at any stage of its conception or production.<\/p>\n<p>This Intellectual Property asset is considered susceptible of registration only if it is totally original, resulting from the intellectual effort of its creator and if\u00a0 it is not commonly known by technicians, specialists or manufacturers, at the moment of its creation.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Validity:<\/strong> 10 years, starting from the date of application filing with Brazilian Patent and Trademark Office or from the date of its first exploitation (whichever occurs first).<\/p>\n<p><strong>Services:<\/strong><\/p>\n<ul>\n<li>Consultancy and strategic legal advice;<\/li>\n<li>Registrability analysis of the set;<\/li>\n<li>Application and renewals for national and foreign registration;<\/li>\n<li>Portfolio acquisition and auditing;<\/li>\n<li>Licensing agreements and ownership transfer;<\/li>\n<li>Dispute of resolutions nationally and internationally;<\/li>\n<li>Administrative proceedings and lawsuits abroad;<\/li>\n<li>Litigation before the State and Federal Courts of Brazil;<\/li>\n<li>Infringement watch committed by third-parties and legal advice on how to contest such infringements; and<\/li>\n<li>Legal Advise on necessary changes to avoid violations as well as legal advice on defense arguments and proceedings.<\/li>\n<\/ul>\n","protected":false},"template":"","class_list":["post-3391","_servicos","type-_servicos","status-publish","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Integrated Circuit Topography - Araripe<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/araripe.com.br\/?_servicos=integrated-circuit-layout-design-protection&lang=en\" \/>\n<meta property=\"og:locale\" content=\"pt_BR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Integrated Circuit Topography - Araripe\" \/>\n<meta property=\"og:description\" content=\"Popularly known as \u201cChip\u201d. It is set of related images codified under any means or form to configure three-dimensionally the layers which compose an integrated circuit. Each image represents the geometric arrangement of the surface of the integrated circuit at any stage of its conception or production. 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